Nuzulan Naim Zulkipli*1, Ahmad Zuri Sha’ameri2, Zulfakar Aspar3 and GhazaliHussin41, 2, 3 Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Johor, MALAYSIA.(E-mail: email@example.com, firstname.lastname@example.org, email@example.com)3 Keysight Technologies Malaysia Sdn. Bhd, Bayan Lepas, Penang, MALAYSIA(E-mail: firstname.lastname@example.org)ABSTRACTError in RF power measurement is due to both additive white Gaussian noise (AWGN) and1/f noise. Thus, the objective of this study is to implement a radio frequency powermeasurement processor on a field programmable gate array (FPGA) to minimize the noisein the signal and improve power measurement accuracy. The processor consists of fivemain modules which are whitening, wavelet decomposition, denoising, signal recovery andpower estimation. The justification for implementation on FPGA is it provides flexibility,reprogrammability and high rate of throughput by exploiting bit parallelism and pipeliningtechniques. The resulting waveforms, RTL notation, and data flow graphs are presentedand compared with Matlab simulations to verify its accuracy, function and performance.Implementation result shows 1.74 % percentage of error at 10 dBm signal power andutilized about 2.84 % logic elements (LE), 3125 out of 110,000.Key words: RF power measurement, FPGA, Wavelet transform, Mallat’s architecture
Radio frequency (RF) power sensor is used to measure the power of various types of signalin the field of communication, aerospace, defence and signal detections. Depending on theapplication, the signal of interest can be either in continuous wave or pulse signals. Tomeet the user specification, the RF power measurement should be conducted with thesmallest possible error .The objective of this paper is to implement an RF power measurement processor in thepresence of 1/f noise. Unlike applications where noise is assumed as additive whiteGaussian noise (AWGN), noise in RF power measurement follows a 1/f power spectrumcharacteristic. This property results in the noise power accumulates at low frequencywhich is at the same frequency of the signal of interest. To reduce power measurementerror, the architecture for the RF power measurement processor is shown in Figure 1.
There are five main modules of the processor which are: whitening, waveletdecomposition, denoising, signal recovery and power estimation. Whitening module isimplemented using decimation of the input signal . In decimation process, the first stepis to analyze the noise at the sensor. From the autocorrelation function of the noise, thedecimation rate for the whitening module is determined. The second step is the waveletdecomposition module where Haar wavelet is used as the basis function and the selecteddecomposition level is five. Mallat’s wavelet decomposition and reconstruction scheme isused for efficient implementation of wavelet transform. At a given decomposition level, apair of low pass filter and high pass filter called quadrature mirror filter (QMF) is used. Byusing integer form as proposed in , detailed coefficients, Dk[n] and approximatecoefficients, Ak[n] can be expressed as()[ ][2 ][2 1]1kA nX n X n=++(1)[ ][2 ][2 1]kD nX n X n=−+(2)Third, denoising is done on the detailed coefficients Dk[n] using universal softthresholding. After that, the signal undergoes signal recovery process to reconstruct thedecomposed signal. Finally, the power in the signal is measured in the power estimationmodule. The complete RF power measurement processor is first verified in Matlabsoftware for its functionality. After that, the proposed processor is plotted in data flowgraph and algorithmic state machine for register transfer level (RTL) transformation. Thefinal step is to implement on FPGA and verified using ModelSIM software.Figure 1. Proposed architecture of RF power measurement processor
To ensure the processor is suitable for real application, the noise (data size 192,000samples) used is obtained from the industry collaborator, Keysight Technologies MalaysiaSdn. Bhd. Figure 2 shows the input and output waveform of the processor implementedon FPGA. The output is obtained after 5,723 cycles: 4,960 cycles for decimation, 251cycles for wavelet decomposition, denoising and reconstruction and 512 cycles forpower estimation. The latency of decimation module depends on the signal length.Longer signals will require more cycles to process. The performance analysis is shownin Table 1. The noise power is a fixed parameter. By varying the signal power, theperformance of the processor is measured by the output of the FPGA implementation.The percentage of error  of the proposed architecture reduced to 1.74% when thesignal power increases. The proposed processor consumed 3125 LE out of 110,000.
Table 1. Performance analysis of FPGA implementationPowerofsignal (W)Powerofsignal (dBm)Power estimated by RF powerprocessor (W)Percentage oferror (%)100 m10.0098.26 m1.74100 µ-10.0097.65 µ2.3582.05 µ-20.8691.55 µ11.59Figure 2. Output waveform of RF power measurement processor
Implementation result shows significant reduction in power measurement error down to1.74 % at 10 dBm signal power and 2.84 % utilization of LE. The implementation took5,723 cycles to complete. As the proposed architecture consumed small amount ofresources of the FPGA, this method can be further developed and analyzed for futureusage.Acknowledgment: We would like to thank Keysight Technologies Sdn. Bhd for theirsupport in this study in term of financial, technical and also raw materials. We would alsolike to express our appreciation to Collaborative Research in Engineering, Science andTechnology (CREST) for providing us with grant P03C1-14 and UTM VOTR.J130000.7323.4B183 which were fully utilized to complete this study.
Assoc. Prof. Dr. Ahmad Zuri bin Sha’ameri obtained his B. Sc. in Electrical Engineering from the University of Missouri-Columbia, USA in 1984, and M. Eng. Electrical Engineering and Ph D both from UTM in 1991 and 2000 respectively. At present, he is a member of the Digital Signal and Image Processing (DSIP) Research Group and Academic Coordinator for the DSP Lab, Electronic and Computer Engineering Department, Faculty of Electrical Engineering, UTM. His research interest includes signal theory, signal processing for radar and communication, signal analysis and classification, and information security. The subjects taught at both undergraduate and postgraduate levels include digital signal processing, advance digital signal processing, advance digital communications and information security. He has also conducted short courses for both government and private sectors. At present, he has published 160 papers in his areas of interest at both national and international levels in conferences and journals.
Besides applications in civil aviation, maritime, defence and homeland security, wireless positioning system has found its use in other variety of applications and services such as enhanced-911, improved fraud detection, location based services, location sensitive billing, intelligent transport systems and improved traﬃc management. Active implementation such radar due with its relatively high transmit power is not suitable for indoor use and has a potential for causing interference or health hazards to potential users. Passive implementation such as global navigation surveillance system (GNSS) has some limitations such as high power consumption, blocking of the RF signal by foliage and buildings. Since the tracked objects usually emit electromagnetic signals, it is possible to perform passive wireless positioning by intercepting and performing analysis on these signals to perform identification based on the signal parameters or information content. By employing multiple receivers, the spatial difference between the intercepted signals can be exploited by estimating the difference between the received signal strength indication (RSSI), angle of arrival (AOA) and time delay of arrival (TDOA) to determine the position of the tracked object. To complete the process, an efficient backbone network should be in place to enable efficient and error free data link between all the receiving stations and a centralized processing system. Current IP based infrastructure and internet of things (IOT) concept can used to form the backbone network for a wireless positioning system.
Despite its benefits, performing a passive wireless positioning system has its own share of challenges. In a noncooperative environment where prior knowledge on the parameters of the possible signals within the band is unknown, among the challenges are noise in the intercepted signal with multipath fading and signals with a combination of the following characteristics: large bandwidth, short duration, and low peak power. Thus, the objective of this presentation is to highlight the possible signal reception technologies through channelized receiver configuration and high speed scanning, signal detection and enhancement with de-noising techniques and the use of time-frequency analysis to estimate the signal parameters for identification. Once identified, the next step is to estimate the position of the tracked object by first estimating the position related parameters such as RSS, AOA or TDOA which is then used by the position estimation process. Field trials results will be presented from the interception of signals at the campus of Universiti Teknologi Malaysia, Johor Bahru and Gunung Raya, Langkawi for automatic dependent surveillance broadcast (ADS-B) signals from aircrafts, short range locating by RSSI fingerprinting and drone locating by TDOA. The results will demonstrate use of wireless positioning for use with different applications.